In semiconductor technology, rapidly shrinking integrated circuit (IC) dimensions drive the requirement of reduced device geometries resulting in the need for multiple voltages to retain compliance with operational constraints. This necessitates the use of on-chip power regulators. In typical applications, the on-chip power regulator derives the supply voltage for the digital core from the input/output (IO) supply voltage. For example, an on-chip regulator generates the 1.2 V supply (for the digital core) from the 3.3 V supply (of the IOs) to save an extra off-chip supply and also to reduce the bill of material (BOM) cost.
In order to facilitate testing, the on-chip regulator is often enabled/disabled by a control signal. This control signal can either be given directly from the IO pad (on the IO ring) or can be driven by the digital core logic itself. However, providing the control signal from the IO ring increases the required number of IO pads resulting in increased cost of packaging.
FIG. 1 illustrates an on-chip control mechanism 100 for on-chip power regulators. The on-chip regulator is controlled by signals which are generated by the digital core. However, since the digital core itself is operating on the Vdd supply generated by the regulator, this may result in unreliable system operation. Further, this approach does not allow the testing of the various sub blocks of the power management unit (PMU).